For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Study of Delay Time on Bit Lines in Megabit SRAM's
Atsushi KINOSHITA Shuji MURAKAMI Yasumasa NISHIMURA Kenji ANAMI
IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
SRAM, coupling capacitance, bit-line,
Full Text: PDF>>
This paper describes the delay time on bit lines due to coupling capacitance between adjacent bit lines in megabit SRAM's. The delay time on bit lines in several generations of megabit SRAM's is quantitatively analyzed using device and circuit simulations. It is shown that narrowing the bit-line swing from 200 mV to 30 mV for future 16-Mbit SRAM's will effectively reduce the difference in delay time from 1.0 ns to 0.3 ns, and that a two-block devided bit line will lower the difference in the delay-time ratio to 3% in case of 15-ns access time.