IEICE Trans - A Timing Calibration Technique for High-Speed Memory Test

A Timing Calibration Technique for High-Speed Memory Test

Mitsuhiro HAMADA  Yasumasa NISHIMURA  Mitsutaka NIIRO

Publication
IEICE TRANSACTIONS on Electronics   Vol.E75-C    No.11    pp.1377-1382
Publication Date: 1992/11/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category:
Keyword:
timing calibration,  IC tester,  timing accuracy,  high-speed memory testing,

Full Text: PDF>>

Summary:
This paper describes a new timing calibration method for IC testers that uses a Timing Calibration Device (TCD). The TCD is a chip fabricated using the same process the device to be tested. Since the TCD has the same assignment pins as the LSI memory device under test (called the "MUT"), it enables an IC tester to evaluate the timing accuracy at the input/output terminal of MUT. The block-select-access time of a 1 K ECL RAM, which is less than 3.0 nanoseconds, has been accurately measured using this device. A timing-calibration subsystem is proposed for IC testers as an application of the TCD. Such a device would achieve precise measurement of high-speed LSI memory devices.