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Soft-Error Immune 180-µm2 SICOS Upward Transistor Memory Cell for Ultra-High-Speed High-Density Bipolar RAMs
Youji IDEI Takeo SHIBA Noriyuki HOMMA Kunihiko YAMAGUCHI Tohru NAKAMURA Takahiro ONAI Youichi TAMAKI Yoshiaki SAKURAI
IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
soft error, SICOS, bipolar RAM, 256 Kbit,
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This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.