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High Speed Data Output Circuit Techniques for a 17 ns 4 Mbit BiCMOS DRAM
Hitoshi MIWA Shoji WADA Yuji YOKOYAMA Masayuki NAKAMURA Tatsuyuki OHTA Toshio MAEDA Masahiro YOSHIDA Hideuki MIYAZAWA Noboru AKIYAMA Kazuyuki MIYAZAWA Jun MURATA
IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
BiCMOS, noise immune, data sense, level shift,
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This 0.8 µm 4 Mbit BiCMOS DRAM achieves the world's fastest chip-enable access time of 17 ns. BiCMOS technology has been employed because of its ability to enhance DRAM performance. Some new circuits, such as a dynamic pull-down type address buffer, a noise immune cascode amplifier, and an offset-cross output circuit are introduced to reduce access time. This paper explains in more detail the noise immune cascode amplifier, and the offset-cross output circuit. A conventional cascode amplifier can operate very rapidly in spite of a heavy parasitic capacitance associated with the data read out line of the memory array. However, when noise, which is inevitably caused by operation, appears on the power supply, bipolar transistors in cascode amplifier cut off, and the cascode amplifier loses its speed advantage. In the noise immune cascode amplifier, a resistor and two capaciters are added to maitain a stable base level of the bipolar transistors. So the cascode amplifier can continue to operate normally, despite the power supply noise. A conventional output circuit is composed of two level converters, four inverters and output transistors. The input swing (the level gap between the data level and the refernce level which are input to the level converters) is 0.5 V, which is not sufficient for the level converter to drive the load capacitance connected with the output transistors. To increase the drivability of the level converter, two 2-stage inverters must be inserted between the level converters and output transistors. In the proposed offset-cross circuit however, the input swing is increased to 1.5 V, which is sufficient for the level converter to drive the load capacitance directly, so the four inverters can be eliminated. The access time is improved by 1.5 ns using the noise immune cascode amplifier, and by 1.7 ns using the offset-cross output circuit. This chip is constructed using a conventional 0.8 µm BiCMOS process. Therefore, it can be used to realize a high speed and low cost memory system.