Stabilization of Voltage Limiter Circuit for High-Density DRAM's Using Pole-Zero Compensation

Hitoshi TANAKA  Masakazu AOKI  Jun ETOH  Masashi HORIGUCHI  Kiyoo ITOH  Kazuhiko KAJIGAYA  Tetsurou MATSUMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.11   pp.1333-1343
Publication Date: 1992/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
memory,  DRAM,  voltage limiter,  pole-zero compensation,  

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Summary: 
To improve the stability and the power supply rejection ratio (PSRR) of the voltage limiter circuit used in high-density DRAM's we present a voltage limiter circuit with pole-zero compensation. Analytical expressions that describe the stability of the circuit are provided for comprehensive consideration of circuit design. Voltage limiters with pole-zero compensation are shown to have excellent performance with respect to the stability, PSRR, and circuit area occupation. The parasitic resistances in internal voltage supply lines, signal transmission lines, and transistors are important parameters determining the stability of pole-zero compensation. Evaluation of a 16-Mbit test device revealed internal voltage fluctuations of 6% during operation of a chip-internal circuit, a phase margin of 53, and a PSRR of 30 dB.