A ST (Stretchable Memory Matrix) DRAM with Multi-Valued Addressing Scheme

Tsukasa OOISHI  Mikio ASAKURA  Hideto HIDAKA  Kazutami ARIMOTO  Kazuyasu FUJISHIMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.11   pp.1323-1332
Publication Date: 1992/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
multi-valued addressing scheme,  

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Summary: 
A multi-valued addressing scheme is proposed for a high speed, high packing density memory system. This scheme is a level-multiplex addressing scheme instead of standard time-multiplex addressing scheme, and provides all address signals to the DRAM at the same time without increasing the address pin counts. This scheme makes memory matrix strechable and achieves the low power dissipation using the enhanced partial array activation. The 16 Mb stretchable memory matrix DRAM (16MbSTDRAM) is examined using this addressing design. A power dissipation of 121.5 mW, access time of 30 ns, and 20 pin have been estimated for 3.3 v 16MbSTDRAM with X/Y=15/9 adress configuration. The low power battery-drive memory system for such as the note-book or the handheld-type personal computers can be realized by the STDRAMs with the multi-valued addressing scheme.