Recessed Memory Array Technology for a Double Cylindrical Stacked Capacitor Cell of 256M DRAM

Kazuhiko SAGARA  Tokuo KURE  Shoji SHUKURI  Jiro YAGAMI  Norio HASEGAWA  Hidekazu GOTO  Hisaomi YAMASHITA  

IEICE TRANSACTIONS on Electronics   Vol.E75-C    No.11    pp.1313-1322
Publication Date: 1992/11/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
recessed memory array,  stacked capacitor cell,  256 MDRAM,  

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This paper describes a novel Recessed Stacked Capacitor (RSTC) structure for 256 Mbit DRAMs, which can realize the requirements for both fine-pattern delineation with limited depth of focus and high cell capacitance. New technologies involved are the RSTC process, 0.25 µm phase-shift lithography and CVD-tungsten plate technology. An experimental memory array has been fabricated with the above technologies and 25 fF/cell capacitance is obtained for the first time in a 0.61.2 µm2 (0.72 µm2) cell.