Four-Valued Dynamic Encoder and Decoder Circuits for CMOS Multivalued Logic Systems

Kazutaka TANIGUCHI  Fumio UENO  Takahiro INOUE  Toshitsugu YAMASHITA  

IEICE TRANSACTIONS on Electronics   Vol.E75-C    No.10    pp.1275-1280
Publication Date: 1992/10/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
multivalued logic,  encoder,  decoder,  

Full Text: PDF(427.9KB)>>
Buy this Article

This paper presents four-valued dynamic encoder and decoder circuits for CMOS multivalued logic systems. The circuits presented here are implemented using a new logical voltage generator and a simplified pass transistor circuit. The logical voltage generator operates with higher speed than the conventional circuit. And the simplified pass transistor circuit contributes to reducing the number of transistors. these circuits have several advantages such as a simple configuration, high speed and low power dissipation. The circuit simulation for the proposed circuits has been performed using SPICE2 program.