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A New Array Architecture for 16 Mb DRAMs with Special Page Mode
Masaki TSUKUDE Tsukasa OISHI Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
array architecture, dynamic memory, high speed access, wide operating margin, low power dissipation,
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An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.