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Performance Evaluation of a Translation Look-Aside Buffer for Highly Integrated Microprocessors
Norio UTSUMI Akifumi NAGAO Tetsuro YOSHIMOTO Ryuichi YAMAGUCHI Jiro MIYAKE Hisakazu EDAMATSU
IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Microprocessors)
Category: RISC Technologies
performance evaluation, TLB, SPARC, PTC, SPEC,
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This paper describes the performance evaluation of the Translation Look-aside Buffer (TLB) for highly integrated microprocessors, especially concerning the TLB in the SPARC Reference MMU specification. The analysis covers configurations, the number of entries, and replacement algorithms for the instruction TLB and the data TLB, which are assumed to be practically integrated on one die. We also present performance improvement using a Page Table Cache (PTC). We evaluate some types of TLB configurations with software simulation and excute the Systems Performance Evaluation Cooperative (SPEC) programs.