A Novel 32-bit RISC Microprocessor for Embedded Systems

Otto MÜLLER  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.10   pp.1196-1201
Publication Date: 1992/10/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Microprocessors)
Category: RISC Technologies
Keyword: 
RISC microprocessor,  embedded systems,  

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Summary: 
The paper describes a novel 32-bit RISC microprocessor architecture for embedded systems. Variable-length instructions of 16, 32 or 48 bits provide compact code since the majority of instructions are 16 bits in length. The basic instruction format of 16 bits allows only 2 register adresses of 5 bits each; however, it is shown that the overhead in the instruction count is only between 14% and is far outweighed by the savings in program size. The register set provides addressing of 16 global and up to max. 16 local registers per stack frame in a register stack of 64 registers. The stack frames are of variable length with a variable overlap for parameter passing. A load/store architecture is used; memory accesses are pipelined. Nearly all instructions execute in a single cycle. A two-stage pipeline (decode/execute) minimizes wait cycles after pipeline breaks due to branches. An instruction cache of 128 bytes employs an efficient look-ahead algorithm and is quickly updated in case of a cache miss. The µP is implemented in 1.2 µm CMOS on a die of 47 mm2. Power dissipation is only 0.5 W. The development environment is PC-based.