N-InAlAs/InGaAs HEMT DCFL Inverter Fabricated Using Pt-Based Gate and Photochemical Dry Etching

Naoki HARADA  Shigeru KURODA  Kohki HIKOSAKA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E75-C   No.10   pp.1165-1171
Publication Date: 1992/10/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Compound Semiconductor Integrated Circuits)
Category: 
Keyword: 
HEMT,  InGaAs,  Schottky junction,  DCEL,  dry etching,  

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Summary: 
A Pt-based gate and photochemical dry etching were developed to fabricate N-InAlAs/InGaAs HEMT ICs. The N-InAlAs/Pt contact showed a Schottky barrier at 0.82 eV, about 0.3 eV larger than ΔEc, and nearly ideal I-V characteristics. Its main disadvantage was the excess penetration of Pt into InAlAs. We proposed a thin-Pt/Ti/Au multilayer gate, more thermally stable than the thick-Pt gate, where Ti layer suppresses the above problem with Pt. The multilayer gate also showed a Schottky barrier (φ) of 0.83 eV and an edeality dactor of 1.1. The high φ value makes it possible to fabricate an E-mode N-InAlAs/InGaAs HEMT. We also developed photochemical selective dry etching using CH3Br gas and a low-pressure mercury lamp. The etching selectivity was 25 at an etch rate of 17 nm/min for InGaAs and 0.7 nm/min for InAlAs. The 1.2-µm-gate E-mode HEMT fabricated using the Pt-based gate and photochemical etching had an excellent peak transconductance of 620 mS/mm with a threshold voltage of +0.03 V. The standard deviation of the threshold voltage of E-mode HEMTs on a 2-inch wafer was 20 mV at an average of +0.088 V. These results indicate the effectiveness of the Pt-based gate and photochemical etching for fabricating N-InAlAs/InGaAs HEMT ICs.