2 switch element. Since each element switches the route accorging to the destination of the input cells, self-routing operation is performed without the external circuit for routing control. The LSI is fabricated using 0.5 µm gate GaAs MESFETs. 7003 logic gate are integrated on the chip of 8.2 mm
For Full-Text PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A GaAs 88 Self-Routing Switch LSI for ATM Switching System
Shouhei SEKI Hiroyuki YAMADA Masanori TSUNOTANI Yoshiaki SANO Yasushi KAWAKAMI Masahiro AKIYAMA
Publication
IEICE TRANSACTIONS on Electronics
Vol.E75-C
No.10
pp.1127-1132
Publication Date: 1992/10/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Compound Semiconductor Integrated Circuits)
Category:
Keyword:
GaAs, B-ISDN, ATM, hardware switch,
Full Text: PDF>>
Summary:
This paper describes the architecture and the performances of a GaAs 88 self-routing switch LSI for ATM switching system. The communication system such as broadband integrated sevices digital network (B-ISDN) requires the hardware switch LSI which exchanges packet cells at a date rate up to several Gb/s. GaAs LSIs are suitable for such application because of its high speed operation and low power dissipation. To clarify the feasibility of GaAs LSI, an 8
8 self-routing switch LSI is fabricated using 0.5 µm gate GaAs MESFETs and its oerformances are examined. This LSI consists of a switching network for exchanging the packet cells and the "NEMAWASHI" network which detects the cell destined to the same output port. The basic network architecture is a self-routing switch using Batcher-Banyan network. This network consists of basic 2
2 switch element. Since each element switches the route accorging to the destination of the input cells, self-routing operation is performed without the external circuit for routing control. The LSI is fabricated using 0.5 µm gate GaAs MESFETs. 7003 logic gate are integrated on the chip of 8.2 mm
7.4 mm. To reduce the impedance of ground line on the chip and to obtain the enough noise margin, the third level interconnection with low sheet resistance is implemented. As the results of functional evalution, the full function of switching network and "NEMAWASHI" network are verified. Maximum operation speed of 1 GHz is obtained.