Thrashing in an Input Buffer Limiting Scheme under Various Node Configurations

Shigeru SHIMAMOTO  Jaidev KANIYIL  Yoshikuni ONOZATO  Shoichi NOGUCHI  

Publication
IEICE TRANSACTIONS on Communications   Vol.E75-B   No.12   pp.1327-1337
Publication Date: 1992/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Teletraffic)
Category: 
Keyword: 
congestion,  queueing networks,  blocking,  class of customers,  finite buffer size,  thrashing,  

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Summary: 
This paper is a study on the behavioral aspects of the input buffer limiting scheme whose basic feature is to award priority to the transit messages over the input messages so that congestion does not develop in the network. The numerical method employed in the analysis is that proposed in Ref.(7). The performance aspects are studied for different buffer capacities, different message handling capacities and different levels of reservation for transit traffic. The numerical method indicates that thrashing occurs at low levels of reservation for the transit messages, irrespective of the buffer size or the processor capacities of the node. This observation is supported by simulation results. With reference to the state-space of the model of our study, the congestion aspects are related to two Liapunov functions. Under the domain of one of the Liapunov functions, the evolution of the perturbed system is towards a congested state whereas, under the domain of the other Liapunov function, the evolution is towards a congestion-free state. Regardless of the configuration, it is found that the fundamental characteristic of the congestion under the input buffer limiting scheme is the characteristic of a fold catastrophe. In the systems with insufficient level of reservation for the transit traffic, the performance degradation appears to be inevitable, irrespective of the capacities of the nodal processor and output channel processor, and the size of the buffer pool. Given such an inevitability, the active life of a node under a typical node configuration is studied by simulation. A suitable performance index is suggested to assess the performance of deadlock-prone nodes.