
For FullText PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.

Linear Time Fault Simulation Algorithm Using a Content Addressable Memory
Nagisa ISHIURA Shuzo YAJIMA
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E75A
No.3
pp.314320 Publication Date: 1992/03/25 Online ISSN:
DOI: Print ISSN: 09168508 Type of Manuscript: INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems) Category: Keyword: fault simulation, content addressable memory, parallel computation,
Full Text: PDF(539.6KB)>>
Summary:
This paper presents a new fast fault simulation algorithm using a content addressable memory, which deals with zerodelay fault simulation of gatelevel synchronous sequential circuits. The computation time of fault simulation for a single vector under the single stuckat fault model is O(n^{2}) for all the existing fault simulation algorithms on a sequential computers. The new algorithm attempts to reduce the computation time by processing many faults at a time by utilizing a property that a content addressable memory can be regarded as an SIMD type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is equivalent to a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.

