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Linear Time Fault Simulation Algorithm Using a Content Addressable Memory
Nagisa ISHIURA Shuzo YAJIMA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Print ISSN: 0916-8508
Type of Manuscript: INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
fault simulation, content addressable memory, parallel computation,
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This paper presents a new fast fault simulation algorithm using a content addressable memory, which deals with zero-delay fault simulation of gate-level synchronous sequential circuits. The computation time of fault simulation for a single vector under the single stuck-at fault model is O(n2) for all the existing fault simulation algorithms on a sequential computers. The new algorithm attempts to reduce the computation time by processing many faults at a time by utilizing a property that a content addressable memory can be regarded as an SIMD type parallel computation machine. According to theoretical estimation, the speed performance of a simulator based on the proposed algorithm is equivalent to a fast fault simulator implemented on a vector supercomputer for a circuit of about 2400 gates.