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An Optimum Placement of Capacitors in the Layout of Switched Capacitor Networks
Mineo KANEKO Kimihiko KAZUI Hiroaki KUNIEDA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/02/25
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Analog Circuits and Signal Processing
analog signal processing, VLSI design technology,
Full Text: PDF(521.2KB)>>
An optimum placement of capacitors in the layout of Switched Capacitor networks is presented in this paper. The performance of integrated circuits is generally degraded by perturbations of physical parameters of each device and parasitic strays. The optimality imposed in this paper is the minimum degradation of a transfer function with respect to the distribution of capacitance values. A capacitance value per unit area fabricated on a LSI chip is assumed to be perturbed linearly with its x and y coordinates. The capacitor placement is determined so that the effects of such perturbation of capacitances to the overall transfer-characteristics are canceled. As the result, input-output transfer function will stay nominal under the linear perturbation model with arbitrary gradients.