A Hierarchical Multi-Layer Global Router

Masayuki HAYASHI  Hiroyoshi YAMAZAKI  Shuji TSUKIYAMA  Nobuyuki NISHIGUCHI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E75-A   No.10   pp.1294-1300
Publication Date: 1992/10/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
global router,  layering,  hierarchical router,  multilayer VLSI,  VLSI CAD,  

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We propose a hierarchical multi-layer global router for Sea-Of-Gates VLSI's, which is different from the conventional global routers, in that routing and layering are executed simultaneously. The main problems to be solved in the global routing for a multi-layer VLSI are which wire segments are laid out on upper layers and how they are connected to terminals located on lower layers. The main objective is to minimize the maximum of local congestions of all layers. We solve these problems in a hierarchical manner by routing from upper layers to lower layers.