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Optimizing and Scheduling DSP Programs for High Performance VLSI Designs
Frederico Buchholz MACIEL Yoshikazu MIYANAGA Koji TOCHINAI
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E75A
No.10
pp.11911201 Publication Date: 1992/10/25
Online ISSN:
DOI:
Print ISSN: 09168508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: highlevel synthesis, optimization, retiming, iteration bound, scheduling,
Full Text: PDF>>
Summary:
The throughput of a parallel execution of a Digital Signal Processing (DSP) algorithm is limited by the iteration bound, which is the minimum period between the start of consecutive iterations. It is given by T_{}=max (T_{i}/D_{i}), where T_{i} and D_{i} are the total time of operations and the number of delays in loop i, respectively. A schedule is said rateoptimal if its iteration period is T_{}. The throughput of a DSP algorithm execution can be increased by reducing the T_{i}'s, which can be done by taking as many operations as possible out of loops without changing the semantic of the calculation. This paper presents an optimization technique, called Loop Shrinking, which reduces the iteration bound this way by using commutativity, associativity and distributivity. Also, this paper presents a scheduling method, called PeriodDriven Scheduling, which gives rateoptimal schedules more efficiently than existing approaches. An implementation of both is then presented for a system in development by the authors. The system shows reduction in the iteration bound near or equal to careful handtunning, and hardwareoptimal designs in most of the cases.

