Hierarchical Module Generation Technique for a High Performance Memory Macrocell

Shigeru DATE  Ken-ichi ENDO  Mitsuyoshi NAGATANI  Junzo YAMADA  

IEICE TRANSACTIONS on Electronics   Vol.E74-C    No.4    pp.938-945
Publication Date: 1991/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: ASIC

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This paper describes the Hierarchical Module Generation Technique capable of creating a high performance memory macrocell. The technique features: (a) automatic generation of macrocells with multi-level hierarchies that achieves the same performance as manually designed macrocells; (b) flexible configuration of macrocells in terms of word-length, bit-width, and cell-shape; and (c) equivalent logic description is created simultaneously with generated patterns that can be used for logic or delay simulation is ASIC design. Several kinds of memory macrocells have been developed as a library including a 1-port RAM, a 2-port RAM, and a ROM using 0.8-µm CMOS technology to verify the effectiveness of this technique.