Logic Functional Level Converter for High Speed Address Decoder of ECL I/O BiCMOS SRAMs

Kazuyuki NAKAMURA  Masahide TAKADA  Toshio TAKESHIMA  Kouichirou FURUTA  Tohru YAMAZAKI  Kiyotaka IMAI  Susumu OHI  Yumi SEKINE  Yukio MINATO  Hisamitsu KIMOTO  

IEICE TRANSACTIONS on Electronics   Vol.E74-C   No.4   pp.845-852
Publication Date: 1991/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: SRAM

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A novel logic functional level converter (FLC) was developed to achieve a high speed ECL I/O BiCMOS SRAM. The FLC simultaneously enables high speed logic operation and ECL to CMOS level conversion. This paper describes an optimized design method for the FLC and an improved FLC. In addition, a high speed partial decoding level converter (PDLC), composed of improved FLCs, is presented. The FLC and a newly developed address decoding sheme with PDLCs, are keys to the successful production of the 5ns 1Mb ECL I/O BiCMOS SRAM.