For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Logic Functional Level Converter for High Speed Address Decoder of ECL I/O BiCMOS SRAMs
Kazuyuki NAKAMURA Masahide TAKADA Toshio TAKESHIMA Kouichirou FURUTA Tohru YAMAZAKI Kiyotaka IMAI Susumu OHI Yumi SEKINE Yukio MINATO Hisamitsu KIMOTO
IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Full Text: PDF>>
A novel logic functional level converter (FLC) was developed to achieve a high speed ECL I/O BiCMOS SRAM. The FLC simultaneously enables high speed logic operation and ECL to CMOS level conversion. This paper describes an optimized design method for the FLC and an improved FLC. In addition, a high speed partial decoding level converter (PDLC), composed of improved FLCs, is presented. The FLC and a newly developed address decoding sheme with PDLCs, are keys to the successful production of the 5ns 1Mb ECL I/O BiCMOS SRAM.