Summary: A novel logic functional level converter (FLC) was developed to achieve a high speed ECL I/O BiCMOS SRAM. The FLC simultaneously enables high speed logic operation and ECL to CMOS level conversion. This paper describes an optimized design method for the FLC and an improved FLC. In addition, a high speed partial decoding level converter (PDLC), composed of improved FLCs, is presented. The FLC and a newly developed address decoding sheme with PDLCs, are keys to the successful production of the 5ns 1Mb ECL I/O BiCMOS SRAM.