Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM

Masanori FUKUMOTO  Yasushi NAITO  Kazuhiro MATSUYAMA  Hisashi OGAWA  Koji MATSUOKA  Takashi HORI  Hiroyuki SAKAI  Ichiro NAKAO  Hisakazu KOTANI  Hiroshi IWASAKI  Michihiro INOUE  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E74-C    No.4    pp.818-826
Publication Date: 1991/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 


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Summary: 
This paper describes a key technology of a small sized stacked capacitor cell to realize 16 MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, which provides reliable contacts with high immunity against process fluctuations such as overetching side-etching and pattern misalignment in photolithography. The cell made by this technology showed desirable characteristics for DRAM operation.