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Leakage Current Reduction in Surrounding Hi-Capacitor DRAM Cell
Geshu FUSE Ichirou NAKAO Yohei ICHIKAWA Chiaki KUDO Toshiki YABU Akito UNO Kazuyuki SAWADA Yasushi NAITO Michihiro INOUE Hiroshi IWASAKI
IEICE TRANSACTIONS on Electronics
Publication Date: 1991/04/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Full Text: PDF(616.1KB)>>
Leakage current in SCC DRAM was reduced by optimizing implant conditions to form channel stopper, node connection and Hi-C boron. To reduce leakage current, the implantation doses should be reduced to reduce implant induced damages. These implant dose reductions are compromised to the necessities of high p type concentration to prevent punch-throughs at several parts of the cell. Near the deep trench bottom, damaged region due to Hi-C boron implant is separated from the bottom edge of the n+ storage node to suppress the gate controlled leakage current. By the improvements, the retention time of the 16 M SCC DRAM becomes over 30 sec at room temperature. It is also shown that folded bit line structure could be adopted easily for SCC.