Reviews and Prospects of DRAM Technology

Yoshinobu NAKAGOME  Kiyoo ITOH  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E74-C   No.4   pp.799-811
Publication Date: 1991/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 


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Summary: 
State-of-the-art dynamic random access memory (DRAM) technologies are reviewed, focusing on circuit design issues. In addition to density increase, clear trends indicated in recent reports are: (1) low-voltage and low-power DRAMs, e.g. a 1.5-3.6 V 64-Mb DRAM and a 4-Mb DRAM with a 3-µA retention current. Lowering the operating voltage is essential in termss of the reliability of miniaturized devices and the power dissipation of the chip. Besides, the resultant low operating current and the low retention current are keys to meeting the increasing demand for battery-backed or battery-operated DRAMs. Important technologies are high-speed sensing, a high-speed low-power internal voltage generator, a word-line booster, and a refresh timer; (2) High-speed DRAMs with half the access times of standard ones, e.g. 17-ns 4-Mb DRAMs. Many efforts have been made to enhance random and serial access rates, such as direct sensing and on-chip interleaving techniques. In addition to high-speed operation, the movement towards larger bit width requires a means of suppressing the noise increased due to a larger peak current. Waveform control for date-line and output charging current is essential; (3) Yield improvement and test cost reduction techniques, e.g. on-chip ECC, parallel testing, and built-in self-testing. These are becoming more and more important for reducing cost.