A 400 MFLOPS FFT Processor VLSI Architecture

Hiroshi MIYANAGA  Hironori YAMAUCHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E74-C   No.11   pp.3845-3851
Publication Date: 1991/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Dedicated Processors
Keyword: 


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Summary: 
We propose a single-chip 400-MFLOPS 2-D FFT processor VLSI architecture. This processor integrates 380,000 transistors in an area of 11.5811.58 mm2 using 0.8 µm CMOS technology with a typical machine cycle time of 25 ns, and executes 2n2n point 2-D FFT in real time, e.g., 256256 point FFT is executed in 14 ms. This excellent performance in terms of both speed and dynamic range makes the real-time processing practical for video as well as speech processing.