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Built-In Self-Test in a 24 Bit Floating Point Digital Signal Processor
Narumi SAKASHITA Hisako SAWAI Eiichi TERAOKA Toshiki FUJIYAMA Tohru KENGAKU Yukihiko SHIMAZU Akiharu TADA Takeshi TOKUDA
IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Dedicated Processors
Full Text: PDF(661KB)>>
A built-in self-test (BIST) based on a signature-analysis (one of the data compression techniques) has been implemented in a 24 bit floating point digital signal processor (DSP). By using only a single pair of linear feedback shift registers (LFSR's) and 253 words of instruction of the DSP, 95% of the functional blocks are self-tested. The number of test patterns is 35 million. It takes only 2.6 seconds for the test at fc26.7 MHz. The overhead of the BIST hardware is about 2.0% of the die size. By comparing the pass rate in a conventional function test to the BIST, nearly the same fault coverage is obtained. This result shows that the BIST is effective for VLSI processors, such as DSPs. By improving this method, manufacturing go/no-go tests without expensive test equipment will be possible.