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Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation
Somchai KITTICHAIKOONKIT Michitaka KAMEYAMA Tatsuo HIGUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Dedicated Processors
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This paper proposes the design of a matrix multiply-addition VLSI processor (MMP) for minimum-delaytime inverse dynamics computation based on linear array architecture. The MMP mainly consists of four multiply-adders, thus performing 44 matrix multiply-additions with a regular data flow. The delay time becomes minimum based on the concept of "odd-even alternative computation". VLSI-oriented architecture which supports high-speed computation of the odd-even alternative computation both in the MMP level and in the array level, is achieved through the use of two types of the data-dependence graphs. By layout evaluation, it is demonstrated that the MMP can be easily implemented in a single chip. A linear array of MMPs is capable of performing inverse dynamics computation of any manipulator with minimum-delay time. The estimated performance with regard to the delay time is the highest in the architectures reported until now.