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An Intelligent Cache Memory Chip Suitable for Logical Inference
Kenichi YASUDA Kiyohiro FURUTANI Atsushi MAEDA Shoichi WAKANO Hiroshi NAKASHIMA Yasutaka TAKEDA Michihiro YAMADA
IEICE TRANSACTIONS on Electronics
Publication Date: 1991/11/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: System VLSI
Full Text: PDF(714.6KB)>>
We have newly developed a VLSI intelligent cache memory chip which constitutes one processor element of a Parallel Inference Machine (PIM/m) system. This cache memory chip contains 610 k transistors including 80 kbits memory cells. The chip measures 14.47 mm14.84 mm and is fabricated by using 1.0µm CMOS double metal technology. The cache memory chip implements a hardware support called "Trail Buffer" which is suitable for the execution of logic programming languages. We have determined the cache memory size by practical simulation taking the relationship between the chip size and hitratio of the cache memory into consideration. The scan test method and the special commands to access every memory cell are applied to enhance the testability. This chip itself operates at a cycle time of 30 MHz. The typical power consumption is 2.5 W with a 5.5 V power supply at 16.7 MHz operation. With this cache memory chip, the CPU board of the PIM/m is now tuned for 16.7 MHz operation and has attained 1.5 MLIPS (logical inference per second), which is the highest performance as an inference machine in the world.