A High Performance 32-Bit Microcontroller for Realtime Applications

Masafumi TAKAHASHI  Yasuo YAMADA  Emi KANEKO  Shinichi YOSHIOKA  Haruyuki TAGO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E74-C   No.11   pp.3766-3774
Publication Date: 1991/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Core and Macrocells
Keyword: 


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Summary: 
A 10-MIPS peak performance single-chip MCU (Micro Controller Unit) core has been developed for real time applications. The following features are implemented to improve cost-effectiveness and the worst interrupt response: (1) large-scale on-chip register with overlapping register windows, (2) the mechanism of receiving exception request with concurrent execution of another instruction, (3) load-store architecture, (4) optimized instruction pipelining, and (5) two 32-bit internal and a 16-bit external buses. It delivers about 5-MIPS average performance in some benchmark programs. The worst overall interrupt response time, which is defined to be the one from receiving an interrupt request to saving the general registers in the invoked interrupt routine, is measured to be 2.38 µs, which is about three fold improvements over a commercial 32-bit MCU. The prototype contains only 15,000 gates, and is cost-effective for 16/32-bit single-chip MCU.