Self-Timed Clocking Design for a Data-Driven Microprocessor

Fumiyasu ASAI
Toshiyuki TAMURA
Hisakazu SATO
Hidehiro TAKATA
Yoshihiro SEGUCHI
Takeshi TOKUDA
Hiroaki TERADA

IEICE TRANSACTIONS on Electronics   Vol.E74-C    No.11    pp.3757-3765
Publication Date: 1991/11/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)
Category: Circuit Design

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This paper details a unique VLSI design scheme which employs self-timed circuits. A 32-bit 50-MFLOPS data-driven microprocessor has been designed using a self-timed clocking scheme. This high performance data-driven microprocessor with sophisticated functions has been designed by a combination of several kinds of self-timed components. All functional blocks in the microprocessor are driven by self-timed clocks. The microprocessor integrates 700,000 devices in a 14.65 mm14.65 mm die area using double polysilicon double metal 0.8 µm CMOS technology.