An Experimental 16 kbit Nonvolatile Random Access Memory

Kazuo KOBAYASHI  Yasushi TERADA  Masanori HAYASHIKOSHI  Takeshi NAKAYAMA  Hideaki ARIMA  Takayuki MATSUKAWA  Tsutomu YOSHIHARA  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E73   No.2   pp.260-264
Publication Date: 1990/02/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 


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Summary: 
High density and high speed nonvolatile random access memory is described. Using the conventional floating gate EEPROM process, a dynamic RAM cell has been merged into an EEPROM cell. Data stored on the DRAM cell can be backed up by the EEPROM cell. The data transfer between the DRAM and the EEPROM is executed simultaneously on all memory cells on a same word line. An experimental 16 kbit memory has been manufactured by 1.5 µm design rule CMOS process. The cell size is 17 µm17 µm and the chip size is 57.2 mm3.75 mm. The address access time of 100 ns and the page read access time of 20 ns have been achieved. A nonvolatile CAM (Content Addressable Memory) cell will also be proposed.