An Analysis of Substrate Current in Memory Cell for ULSI SRAM

Yoshiyuki HARAGUCHI  Shuji MURAKAMI  Yasumasa NISHIMURA  Kenji ANAMI  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E73   No.11   pp.1861-1862
Publication Date: 1990/11/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits
Keyword: 


Full Text: PDF(133.6KB)>>
Buy this Article




Summary: 
We analyze the substrate corrent of submicron transistors in the memory cell of ULSI SRAMs in the cases of PMOS and NMOS bit line loads. The lifetime of the transistors is also estimated. The SRAM using an NMOS bit load is found to be better as a hot carrier than that with a PMOS bit load.