A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's

Hirotoshi SATO  Shuji MURAKAMI  Yasumasa NISHIMURA  Toshihiko HIROSE  Kenji ANAMI  

IEICE TRANSACTIONS (1976-1990)   Vol.E73   No.11   pp.1858-1860
Publication Date: 1990/11/25
Online ISSN: 
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Integrated Circuits

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Delay time and power consumption, serious problems in high-density SRAM's are simulated over several generations with the HWD architecture. The optimum grade of hierarchy is obtaind for 64 kbit to 256 Mbit SRAM's.