An Architecture for FFT Butterfly Computation with Merged Core Multiplication technique

Farhad Fuad ISLAM  Hiroto YASUURA  Keikichi TAMARU  

IEICE TRANSACTIONS (1976-1990)   Vol.E73   No.11   pp.1810-1812
Publication Date: 1990/11/25
Online ISSN: 
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category: Signals, Circuits and Images

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An architecture for radix-2, decimation in frequency fast Fourier transform butterfly computation unit is proposed. It operates on 16 bit inputs and uses 'merged core' type of multipliers which reduce hardware components and hence promise smaller chip area. This reduction in area is achieved with negligible increase in computation delay.