Some Properties of the Perfect Shuffle Interconnection for Parallel Computations

Takeshi KUMAGAI  Takanobu BABA  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E72    No.9    pp.998-1002
Publication Date: 1989/09/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: PAPER
Category: Computer Networks
Keyword: 


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Summary: 
The perfect shuffle interconnection is widely used in parallel processing hardware, mostly in multistage configurations. However it is rarely applied to VLSI arrays except for the case of realizing FFT or sorting. This is due to the fact that control methods to load data into cells have not been established yet. VLSI arrays using the interconnection have a potential possibility to realize some kinds of computations more efficiently than ones using other interconnections. This paper analyzes properties of the perfect shuffle interconnection to apply it to parallel computations by VLSI arrays, especially existence of a cell into which a given pair of inputs are loaded and a control method to make pairs on cells are discussed. The properties presented become basis to realize parallel computations by VLSI arrays using the perfect shuffle interconnection.