2-GHz 8-Stage Synchronous Counter Using 400-Gate SST Bipolar Macrocell Array

Naoaki YAMANAKA  Masao SUZUKI  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E72   No.8   pp.885-887
Publication Date: 1989/08/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: LETTER
Category: Electronic Circuits
Keyword: 


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Summary: 
This letter presents the development of a high-speed 8-stage synchronous counter LSI which uses a 400-gate macrocell array. The LSI uses a sophisticated low-voltage-swing differential CML circuit technique and super-self-aligned Si-bipolar process technology (SST). The counter operates at up to 2 GHz with a chip power dissipation of 0.91 W.