Performance Improvement of All Digital Phase-Locked Loop with Adaptive Multilevel-Quantized Phase Comparator

Osamu NAKAJIMA  Hiroomi HIKAWA  Shinsaku MORI  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E72   No.3   pp.194-201
Publication Date: 1989/03/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: PAPER
Category: Communication Systems and Transmission Equipment
Keyword: 


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Summary: 
A new type of phase comparator for DPLL (Digital Phase-Locked Loop), named Adaptive Multilevel-Quantized Phase Comparator (abbreviated as AMPC), is proposed. The characteristics of this proposed comparator AMPC are changed adaptively to reduce the frequency deviation and the phase jitter of the input signals, whereas the conventional phase comparator has constant characteristics whatever signals come. When the offset between input and output signal frequency exists, the amount of frequency control is increased by shifting up or down its characteristics in order to decrease this deviation. When the loop is in the steady-state, the amount of phase control is decreased by varying the scale of them to suppress the input jitter. Performance characteristics of AMPC and the loop which uses AMPC are analyzed theoretically and verified by computer simulation. As a result, the loop which uses AMPC has much wider locking-range and much better jitter suppresion effect than those of the conventional loops, and steady-state phase error is also reduced by using AMPC.