Performance Improvement of MS Synchronization Networks with Increased Averaging Numbers along Hierarchy

Zaihua LUAN  Shinsaku MORI  

IEICE TRANSACTIONS (1976-1990)   Vol.E72   No.12   pp.1432-1438
Publication Date: 1989/12/25
Online ISSN: 
Print ISSN: 0000-0000
Type of Manuscript: PAPER
Category: Communication Systems and Transmission Equipment

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This paper proposes a hierarchical MS synchronization network in which the slaves increased averaging numbers of phase errors along the hierarchy in order to improve the network characteristics in both jitter suppression and phase tracking. The properties of the proposed network are investigated and compared with the conventional one which uses an identical averaging number in all hierarchical slaves. The results show the proposed network has an advantage over the conventional one. With the same tracking property, the jitter accumulation in the network proposed with 9 hierarchies is suppressed about 0.8-2 dB more than that in the conventional identical one, and much higher improvements are guaranteed in a larger hierarchical MS network. The idea of using increased averaging numbers along the hierarchy can be applied to the general MS synchronization network which consists of a chain of PLLs, for instance, one can design the transfer function of the PLLs with the reduced bandwidth along the chain, to obtain a better performance in the network entirety than the conventional identical one.