Level Shift Circuits for GaAs Low Power Source Coupled FET Logic

Masanobu OHHATA  Tohru TAKADA  Masayuki INO  Masao IDA  

IEICE TRANSACTIONS (1976-1990)   Vol.E70   No.4   pp.224-226
Publication Date: 1987/04/25
Online ISSN: 
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1987 National Convention IEICE)
Category: Semiconductor Devices and Integrated Circuits

Full Text: PDF(194.7KB)>>
Buy this Article

A novel level shift circuit for Low Power Source Coupled FET Logic (LSCFL) is proposed that effectively lowers the power supply voltage. Master-slave T-type flip-flops (T-FFs) with reset function using a three level series gate are designed employing the new level shift circuit, and fabricated using the BP-SAINT process. It is demonstrated that this advanced T-FF operates with a power supply voltage of -1.8 V, which is 30% less voltage than the conventional LSCFL.