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GaAs Universal Multiplexer/demultiplexer using LSCFL
Tohru TAKADA Kazuhiko NOZAWA Masao IDA Kazuyoshi ASAI
IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/04/25
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan)
Category: Compound Semiconductor Devices
Full Text: PDF(345.4KB)>>
The high speed and low power GaAs LSI is developed for application to a Giga bit rate digital data switching system using Low Power Source Coupled FET Logic. This LSI has functions of multiplexing, demultiplexing, frame pulse generation and three-stage counting. Eight and four bits operations over 1.3 Gbit/s data rate with less than 0.75 W power dissipation are achieved.