On-Chip Testing for 30 K-Gate Masterslice

Shinji SATO  Hiromasa TAKAHASHI  Yasuhide MACHIDA  Gensuke GOTO  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E69   No.4   pp.267-269
Publication Date: 1986/04/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan)
Category: Silicon Devices and Integrated Circuits
Keyword: 


Full Text: PDF>>
Buy this Article




Summary: 
On-chip testing for 30 K-gate masterslice with freely configured SRAM AND/OR ROM blocks was investigated. Multiplier fault coverage was about 93 percent. The validity of on-chip testing was confirmed in masterslices containing over 20 K gates with memory blocks.