A 6 NS 16 Bit Parallel Multiplier Using an SST Macrocell Array

Masao SUZUKI  Shinsuke KONAKA  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E69   No.4   pp.264-266
Publication Date: 1986/04/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan)
Category: Silicon Devices and Integrated Circuits
Keyword: 


Full Text: PDF(346.7KB)>>
Buy this Article




Summary: 
A 16 bit parallel parallel multiplier is developed by using LCML macrocell circuit design and an improved SST macrocell array with a 0.35 µm emitter width. This multiplier consists of carry-save and carry-lookahead adders. A 6 ns multiplication time is achieved 1.93 W/chip.