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A 6 NS 16 Bit Parallel Multiplier Using an SST Macrocell Array
Masao SUZUKI Shinsuke KONAKA
IEICE TRANSACTIONS (1976-1990)
Publication Date: 1986/04/25
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan)
Category: Silicon Devices and Integrated Circuits
Full Text: PDF(346.7KB)>>
A 16 bit parallel parallel multiplier is developed by using LCML macrocell circuit design and an improved SST macrocell array with a 0.35 µm emitter width. This multiplier consists of carry-save and carry-lookahead adders. A 6 ns multiplication time is achieved 1.93 W/chip.