CMOS Radix-2 Signed-Digit Adder by Binary Code Representation

Tadashi NAKANISHI  Hironori YAMAUCHI  Hiroshi YOSHIMURA  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E69   No.4   pp.261-263
Publication Date: 1986/04/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan)
Category: Silicon Devices and Integrated Circuits
Keyword: 


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Summary: 
Binary code representation successfully reducing device count for radix-2 Signed-Digit arithmetic has been proposed and an adder using this binary code has been designed. Delay time of addition is estimated at 5.5 ns regardless of digit length using 1.2 µm CMOS technology. The occupied area is almost the same compared with CLA.