High-Speed Integrated Optical Repeater Design Method

Mamoru AIKI  Toshiyuki TSUCHIYA  Tsutomu KAMOTO  

IEICE TRANSACTIONS (1976-1990)   Vol.E69   No.2   pp.113-123
Publication Date: 1986/02/25
Online ISSN: 
Print ISSN: 0000-0000
Type of Manuscript: PAPER
Category: Communication Systems and Communication Protocols

Full Text: PDF>>
Buy this Article

This paper describes a design method for a 446 Mb/s optical repeater with four kinds of monolithic integrated circuits. It is mainly concerned with the circuit division, optical receiver and timing amplifier design methods. Repeater circuit is divided based on maximum allowable gain and power consumption. Allowable gain determined by IC package crosstalk characteristics at 400 MHz transmission band is presented here. Allowable maximum power consumption of 1 W/chip is also determined. Effective amplification bandwidth adjustment methods for the optical receiver and the d.c. drift control (DCFB) system design method, specific in the d.c. coupled monolithic integrated optical receiver, are described. Finally, a useful design method for small-phase-shift timing amplifier is proposed. This is a circuit parameter optimizing method which monitors operating point dependence of small signal amplification bandwidth. The 446 Mbit/s submerged optical repeater has successfully been developed using these design methods.