High-Speed Time Division Switch Operating at 256 Mb/s

Naoaki YAMANAKA  Masaharu KAWAKAMI  Yasukazu TERADA  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E68   No.9   pp.570-571
Publication Date: 1985/09/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: LETTER
Category: Switching Systems
Keyword: 


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Summary: 
This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100 K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s64 channels) are obtained.