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High-Speed Time Division Switch Operating at 256 Mb/s
Naoaki YAMANAKA Masaharu KAWAKAMI Yasukazu TERADA
IEICE TRANSACTIONS (1976-1990)
Publication Date: 1985/09/25
Print ISSN: 0000-0000
Type of Manuscript: LETTER
Category: Switching Systems
Full Text: PDF(157KB)>>
This letter presents the construction of a high-speed time division switching system for the video network, using Si-bipolar super-high-speed RAMs and ECL 100 K families. A switching speed of 256 Mb/s and a switching throughput of 2 Gb/s (signal speed 32 Mb/s64 channels) are obtained.