Analysis of an Access Contention Model in a Multiprocessor-Controlled Switching System

Shuichi SUMITA  

IEICE TRANSACTIONS (1976-1990)   Vol.E68   No.12   pp.824-830
Publication Date: 1985/12/25
Online ISSN: 
Print ISSN: 0000-0000
Type of Manuscript: PAPER
Category: Switching Systems

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This paper presents a queueing network model for common memory access contention and access contention to common data that cannot be referenced by more than one processor in a multiprocessor-controlled switching system. The model takes into account the inter-dependence between these types of access contention, which is important for evaluating the performance of a single-bus multiprocessor system. Although this inter-dependence is incorporated into the queueing network model, an exact analysis is difficult. Therefore, an approximate analysis method is proposed based on decomposing the model into two submodels. Approximate analysis results are compared with simulation results and it is shown that the approximation method provides sufficient approximate values. This queuing network model is useful for estimating the call processing capacity of a multiprocessor-controlled switching system.