Paralle Merge Algorithm Suitable for VLSI Implementation

Shin'ichi WAKABAYASHI  Tohru KIKUNO  Noriyoshi YOSHIDA  

IEICE TRANSACTIONS (1976-1990)   Vol.E67   No.4   pp.234-235
Publication Date: 1984/04/25
Online ISSN: 
Print ISSN: 0000-0000
Type of Manuscript: LETTER
Category: VLSI Algorithms

Full Text: PDF(132.5KB)>>
Buy this Article

A new parallel merge algorithm suitable for VLSI implementation is proposed. This algorithm can merge a given set of sorted sequences in O (N) computation time, where N is a total number of keys in input sequences, and it works on a linear array of simple identical processors.