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Failure Rate Prediction Method for LSIs
Kiyoshi OGAWA Yoshimitsu SAKAGAWA Yoshio SUNOHARA
IEICE TRANSACTIONS (1976-1990)
Publication Date: 1983/09/25
Print ISSN: 0000-0000
Type of Manuscript: PAPER
Category: Integrated Circuits
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This paper proposes, as a new LSI reliability estimation method, a procedure for estimating the failure rate of LSI by classifying failures according to failure modes and by expressing the failure rates as functions of the LSI design parameters. As a concrete example, bipolar logic LSIs and MOSRAMs were taken up. Their respective failure modes and the design parameter dependences for the failure rates were considered, in order to obtain the relations between the integration density and the failures. As a result, it was clarified that the failure rate per gate for bipolar logic LSI was inversely proportional to (the number of gates)0.4 and that the failure rate per bit for MOSRAM was inversely proportional to (the number of bits)0.7. And it was concluded that the dominant failure modes will be in the metallization for the bipolar logic LSI and in surface degradation for the MOSRAM. Thus, new LSI reliability estimation was carried out. And the technical problems to solve or new technical targets to study in order to improve the reliability of high density LSIs were clarified.