A 65 Kbit Dynamic RAM Using Short Channel MOS FETs

Masahide TAKADA  Toshio TAKESHIMA  Shunichi SUZUKI  Mitsuru SAKAMOTO  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E62   No.7   pp.484-485
Publication Date: 1979/07/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: LETTER
Category: Integrated Circuits
Keyword: 


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Summary: 
A 65 Kbit dynamic MOSRAM has been realized using short channel and single-level Si-gate technologies and a newly designed, highly sensitive and low power dissipation sense amplifier. Access time and power dissipation are 150 ns and 120 mW, respectively.