The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System

Tomoki SHIMIZU
Kohei ITO
Kensuke IIZUKA
Kazuei HIRONAKA
Hideharu AMANO

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E105-D    No.12    pp.2008-2018
Publication Date: 2022/12/01
Publicized: 2022/06/30
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2022PAP0009
Type of Manuscript: Special Section PAPER (Special Section on Forefront Computing)
Category: 
Keyword: 
FPGA,  multi-FPGA systems,  interconnection network,  packet switching,  TDM,  parallel computer,  

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Summary: 
The multi-FPGA system known as, the Flow-in-Cloud (FiC) system, is composed of mid-range FPGAs that are directly interconnected by high-speed serial links. FiC is currently being developed as a server for multi-access edge computing (MEC), which is one of the core technologies of 5G. Because the applications of MEC are sometimes timing-critical, a static time division multiplexing (STDM) network has been used on FiC. However, the STDM network exhibits the disadvantage of decreasing link utilization, especially under light traffic. To solve this problem, we propose a hybrid router that combines packet switching for low-priority communication and STDM for high-priority communication. In our hybrid network, the packet switching uses slots that are unused by the STDM; therefore, best-effort communication by packet switching and QoS guarantee communication by the STDM can be used simultaneously. Furthermore, to improve each link utilization under a low network traffic load, we propose a dynamic communication switching algorithm. In our algorithm, each router monitors the network load metrics, and according to the metrics, timing-critical tasks select the STDM according to the metrics only when congestion occurs. This can achieve both QoS guarantee and efficient utilization of each link with a small resource overhead. In our evaluation, the dynamic algorithm was up to 24.6% faster on the execution time with a high network load compared to the packet switching on a real multi-FPGA system with 24 boards.